1. Field of the Invention
The invention relates to the field of integrated circuits including gating means, memories and calculators and more particularly to the conditional modification of four phase gates, the modification of memory architecture and the obtaining of calculators with differing capabilities from a common integrated circuit component configuration.
2. Description of Prior Art
Many prior art conditional modification systems are known which modify the output signal from a gate in accordance with whether other output signals from other gates satisfy a predetermined condition. However, such prior art modification systems employ an additional set of gates which, in a clocked gating system, requires an additional clock phase time in which to modify the gate output. The consumption of an additional phase time has the disadvantage that it increases the time required to complete a calculation or function. Also where a circuit has been designed to operate with a specified number of phase times, the subsequent addition of conditional modification cannot be accomplished without increasing the number of phase times required for the operation of the gating circuit. The prior art increased phase time for modification prevents minor modifications from being added to existing gating systems without major redesign. Further, the use of an additional phase time clearly increases the time required to perform any system function or routine.
A number of multipurpose integrated circuit chips are known in the prior art. These chips are provided with the ability to perform one of many functions. The function actually performed is determined by the way in which the individual circuits on the chip are interconnected by the on-chip metallization. These circuits, however, are often wasteful of space as a result of a customization of the circuit which leaves many of the individual circuits unconnected and unused. Also, such chips often result in an inefficient layout of the components actually employed in the final circuit. Further, complicated metallizations are often required to achieve the desired function. Consequently, these circuits severely compromise efficient utilization of chip area in order to obtain great modification flexibility. In addition, maximum circuit efficiency is often sacrificed in modifying such general purpose semiconductor chips to perform a designed function because the devices present on the chip are not those best suited for performance of the function.
Thus, although the prior art systems are useful in some instances, they leave much to be desired in the way of system and material efficiency.
In order to minimize the cost and complexity of solid state calculators, or the like, it is frequently desirable to build the memory and related logic circuitry on a single semiconductor chip. Memories tend to be relatively long compared to their width. Therefore the physical relative dimensions of the memory often hinder maximum efficiency in the layout of logic circuitry. This leads to further inefficiency in the use of material and to an extent of logic circuitry in the production of a modifiable calculator, since the memory dimension may force a contorted layout of the logic circuitry in order to obtain maximum use of the chip.